Title :
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
Author :
Singh, Adit D. ; Sogomonyan, Egor S. ; Gossel, Michael ; Seuring, Markus
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
Abstract :
The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with a full scan capability to support custom test vectors, diagnosis, and design debugging. A key feature is the ability to support pseudorandom at-speed delay testing of the functional circuit paths without imposing any performance penalty on the design beyond that for traditional scan. This paper presents a CMOS design for the MSME, and investigates benchmark circuits designed with this memory element. The results show that very high stuck-at and transition delay test coverage can be achieved for most cases using the pseudorandom self-test mode alone. Evaluation of layouts indicates low to moderate area overhead
Keywords :
CMOS digital integrated circuits; built-in self test; design for testability; fault diagnosis; integrated circuit layout; integrated circuit testing; logic simulation; logic testing; sequential circuits; CMOS design; area overhead; benchmark circuits; circular self-test path approach; custom test vectors; design debugging; design-for-test technique; diagnosis; full scan capability; functional circuit paths; layout evaluation; multi-mode scannable memory element; pseudorandom at-speed delay testing; sequential designs; stuck-at fault test coverage; testability evaluation; transition delay test coverage; Automatic testing; Benchmark testing; Built-in self-test; Circuit testing; Clocks; Crosstalk; Debugging; Delay effects; Sequential analysis; System testing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805642
