Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm

Author

Nakahara, Shigeru ; Higeta, Keiichi ; Kohno, Masaki ; Kawamura, Toshiaki ; Kakitani, Keizo

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1999

fDate

1999

Firstpage

301

Lastpage

310

Abstract

This paper presents a built-in self-test (BIST) scheme, which consists of a flexible pattern generator and a practical on-macro two-dimensional redundancy analyzer, for GHz embedded SRAMs. In order to meet the system requirements and to detect a wide variety of faults or performance degradation resulting from recent technology advances, the microcode-based pattern generator can generate flexible patterns. A practical new repair algorithm for the Finite State Machine (FSM)-based on-macro redundancy analyzer is also presented. It can be implemented with simple hardware and can show fairly good performance compared with conventional software-based algorithms

Keywords

CMOS memory circuits; SRAM chips; automatic test pattern generation; built-in self test; embedded systems; emitter-coupled logic; fault diagnosis; finite state machines; integrated circuit testing; redundancy; BIST scheme; ECL-CMOS SRAMs; FSM-based on-macro redundancy analyzer; GHz embedded SRAMs; fault detection; flexible pattern generator; microcode-based pattern generator; on-macro two-dimensional redundancy analyzer; performance degradation; repair algorithm; Automata; Built-in self-test; Circuit faults; Circuit testing; Degradation; Hardware; Pattern analysis; Random access memory; Redundancy; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805644

Filename

805644