Title :
Low power implementation of DCT for on-board satellite image processing systems
Author :
Vijay, S. ; Anchit, D.
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Abstract :
Full adders are the significant elements which need to be analyzed for low-complexity implementation. Algorithms which minimize the complexity of multiplications of the input image matrix and the DCT matrix focus on reducing the number of full adders (NFAs) needed to implement the multiplication. In this paper, we have successfully proposed a novel technique to reduce considerably the NFAs, and thereby both the power consumption and time delay involved in implementing the image-DCT multiplication. The authors make use of row-column transformations of the input image matrix exploiting the symmetry of the DCT. Design results show that our method gives an average reduction in power of about 10.5% when compared to differential pixel implementation (DPI) and 16.5% when compared to the conventional implementation. The proposed method can also be made recursive, which can further reduce the NFAs for the implementation.
Keywords :
computer vision; discrete cosine transforms; geographic information systems; image resolution; matrix algebra; remote sensing; differential pixel; discrete cosine transform; input image matrix; multiplications complexity; on-board satellite image processing systems; power consumption; Adders; Discrete cosine transforms; Discrete transforms; Image coding; Image processing; Pixel; Remote sensing; Satellite ground stations; Sparse matrices; Transform coding; Differential pixel; Discrete Cosine Transform; low-power;
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2009.5235883