Programmable low-density parity-check decoder

This paper presents a programmable semi-parallel architecture for low-density parity-check (LDPC) codes. Communication conflicts are avoided by edge-coloring the code graph and grouping of edges/physical connections by color. The architecture model is easily scalable and programmable for larger block sizes. Though the communication hardware cost is high, the model can be easily reconfigured to reduce hardware cost at the expense of flexibility in code design and decoding performance. The hardware cost, latency, code flexibility and code performance tradeoffs can be varied over a wide range to suit a wide range of applications. Simple execution control and mapping are other advantages of this model. A behavioral VHDL implementation was developed to verify the functionality of the architecture.