Title :
On a gate sizing of multiple-paths circuit for optimizing power-delay
Author :
Seung Ho Lee ; Jong Kwon Chang
Author_Institution :
Dept. of Electr. Eng., Univ. of Ulsan, Ulsan, South Korea
Abstract :
Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. In the previous work, the method of optimizing power-delay efficiency in a logical path showed about 40% greater efficiency in power dissipation than the existing technique. However, our previous technique is constrained for a single logical path. In this paper, we extend it for a multiple logical paths and thus, determine the gate size according to the formula derived in this paper.
Keywords :
delay circuits; logic circuits; logic design; optimisation; design cycle time; gate sizing; logical effort; multiple-paths circuit; power delay optimisation; power dissipation; quick delay estimation; Capacitance; Delay; Equations; Integrated circuits; Logic gates; TV; Transistors; Logical Effort; capacitive transformation equation; equal delay model; multiple paths gate sizing; power-delay efficiency;
Conference_Titel :
Strategic Technology (IFOST), 2011 6th International Forum on
Conference_Location :
Harbin, Heilongjiang
Print_ISBN :
978-1-4577-0398-0
DOI :
10.1109/IFOST.2011.6021107
