DocumentCode :
3329665
Title :
The research of low-power design method based on SOC test controller
Author :
Gu Jing ; Guibo Han ; Yu Xiaoyang
Author_Institution :
Inst. of Comput. Sci. & Technol., Harbin Univ. of Sci. & Technol., Harbin, China
Volume :
2
fYear :
2011
fDate :
22-24 Aug. 2011
Firstpage :
690
Lastpage :
694
Abstract :
Considered from the test structure, test time, test power, the paper based on the IEEEstd1500 standards, the first reference in the test circuit is to build a structure of SOC testing, including test cases and test shell test controller., SOCd695 were completed by SOC test scheduling TAM through Optimization of neural network after simulation. In order to achieve optimal low-power SOC design of the tcu test control unit, use the adoption of innovative parity algorithm in descending order before test scheduling, to to reduce the testing of all nodes in the transition activities to reduce the power consumption of SOC test structure. Experimental results show that this method is better to reduce power consumption, lower the cost of test.
Keywords :
IEEE standards; cost reduction; electronic engineering computing; integrated circuit design; integrated circuit testing; neural nets; scheduling; system-on-chip; IEEEstd1500 standard; SOC test controller; SOC test scheduling TAM; SOCd695; low-power design method; neural network; parity algorithm; test access mechanism; test circuit; test shell test controller; testing cost reduction; Capacitance; Energy consumption; Integrated circuit modeling; Loading; System-on-a-chip; Testing; Benchmark circuits; Low power consumption; Parity algorithm in descending order of dl; Test Controller;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Strategic Technology (IFOST), 2011 6th International Forum on
Conference_Location :
Harbin, Heilongjiang
Print_ISBN :
978-1-4577-0398-0
Type :
conf
DOI :
10.1109/IFOST.2011.6021118
Filename :
6021118
Link To Document :
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