VHDL Based FPGA Implementation of 256-ary PPM for Free Space Optical Links

Author

Muhammad, S. Sheikh ; Brandl, P. ; Leitgeb, E. ; Koudelka, O. ; Jelovcan, I.

Author_Institution

Inst. of Broadband Commun., Graz

Volume

3

fYear

2007

fDate

1-5 July 2007

Firstpage

174

Lastpage

177

Abstract

As the interest in the deployment of Free Space Optical (FSO) links gains momentum, its becoming important to investigate the implementation of proposed higher state modulation schemes. M-ary PPM promises significant performance enhancement and this paper gives results about an experimental VHDL based FPGA implementation of a 256-ary PPM modem. The discussed chip design proves the capability of M-ary PPM as an implementable solution for future FSO systems. This preliminary design provides a suitable starting point for an integrated solution in the next generation FSO systems.

Keywords

field programmable gate arrays; hardware description languages; optical links; pulse position modulation; 256-ary PPM modem; FPGA; M-ary PPM; VHDL; chip design; field programmable gate arrays; free space optical link; pulse position modulation; Clocks; Field programmable gate arrays; Optical fiber communication; Optical modulation; Optical pulses; Optical receivers; Optical transmitters; Pulse modulation; Synchronization; Timing; FPGA implementation; Free Space Optics (FSO); M-ary PPM;

fLanguage

English

Publisher

ieee

Conference_Titel

Transparent Optical Networks, 2007. ICTON '07. 9th International Conference on

Conference_Location

Rome

Print_ISBN

1-4244-1249-8

Electronic_ISBN

1-4244-1249-8

Type

conf

DOI

10.1109/ICTON.2007.4296273

Filename

4296273