Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking

Radiation-induced soft errors on large-scale integrated circuits are becoming increasingly problematic as device sizes are scaled down, operating voltages are reduced, and node capacitances shrink. Therefore, chip reliability has become a big issue in modern VLSI design and the importance of detecting soft error in combinational logic circuits has been recognized. In this paper a method incorporating two error detecting methods, parity check and shadow latch, is presented. The results show that the proposed method combines the best of both previously proposed methods and achieves the soft error rate reduction of 70% with 50% cost overhead for random logic blocks, providing a better cost return for using either method along.