Title :
An embedded technique for at-speed interconnect testing
Author :
Nadeau-Dostie, Benoit ; Cote, Jean-Francois ; Hulvershorn, Harry ; Pateras, Stephen
Author_Institution :
Logic Vision Canada Inc., Ottawa, Ont., Canada
Abstract :
A new embedded test technique which provides full at-speed testing of board level interconnect is described. The proposed technique is fully compatible with the IEEE 1149.1 boundary scan standard. The technique extends the standard´s architecture to provide for synchronized at-speed timing control of the boundary scan cells so that test data can be applied and captured across the interconnect at system speeds
Keywords :
IEEE standards; automatic testing; boundary scan testing; integrated circuit interconnections; integrated circuit testing; printed circuit testing; synchronisation; timing; IEEE 1149.1 boundary scan standard; architecture; at-speed interconnect testing; board level architecture; board level interconnect; boundary scan cells; embedded technique; high level architecture; synchronisation; Delay; Frequency; Hardware; Manufacturing; Packaging; Performance evaluation; Pins; Probes; System testing; Timing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805765
