Testing faults in SRAM memory of Virtex-4 FPGA

Various algorithms and testing schemes have been developed in the past for testing memories for the presence of faults. Due to the increasing popularity of FPGAs, some schemes have specifically been developed for testing memories in these devices. FPGAs, when used in airborne space applications, are exposed to radiations which can produce faults within their memory. Faults may also develop during the manufacturing process. In the past, testing embedded memories within Field Programmable Gate Arrays has been limited to the detection of stuck-at faults. Recent studies have shown that FPGA memories are also prone to address decoder, transient, and inversion coupling faults. To address these faults, the current research proposes to develop a Built-in Self Test (BIST) technique for testing embedded SRAM memories of Virtex-4 FPGAs for the presence of address decoder, inverse coupling, transient and also stuck-at faults. The technique is modeled using VHDL. Simulation results are presented to verify fault detection.