Interconnect delay fault testing with IEEE 1149.1

In high speed systems, the AC performance of interconnects on boards and backplanes are critical. Today, most companies rely on functional test vectors to conduct interconnect delay fault tests. Besides poor fault coverage, this approach does not provide much diagnostic information when faults are detected. Based on the concept of early capture and late update, this paper proposes a novel technique to conduct board interconnect delay fault test using a IEEE 1149.1 standard TAP controller. The proposed technique does not require any extra pin to ASICs, does not require any modification of standard boundary scan cells and uses a standard TAP controller. The costs of the proposed technique include only a few flip-flops plus some gates in a TAP controller wrapper without modification of the standard TAP controller itself