Title :
Optimal conditions for Boolean and current detection of floating gate faults
Author :
Renovell, M. ; Ivanov, A. ; Bertrand, Y. ; Azais, F. ; Rafiq, S.
Author_Institution :
LIRMM, CNRS, Montpellier, France
Abstract :
This paper studies the Boolean (Static Voltage) and the Iddq (Static Current) detection of Floating Gate faults due to large opens on transistor gate connections. We show that existing electrical models describing the behavior of FGT faults fail to allow the prediction of the floating gate potential due to the unpredictable parameters such as the initial changes and the polysilicon-to-bulk capacitance. We propose the twin-transistor structure as a basis for a general analysis of the Boolean and Iddq detection of FGT faults. Using this analysis, optimal conditions for detection are defined for Boolean as well as Iddq tests
Keywords :
Boolean functions; electric current measurement; fault diagnosis; integrated circuit testing; logic gates; logic testing; production testing; voltage measurement; Boolean detection; FGT faults; Iddq tests; cost; current detection; floating gate faults; floating gate potential; initial changes; large opens; logic testing; optimal conditions; polysilicon-to-bulk capacitance; static voltage; transistor gate connections; twin-transistor structure; Capacitance; Circuit faults; Delay; Electrical fault detection; Fault detection; Integrated circuit testing; Manufacturing; Predictive models; Tunneling; Voltage;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805770
