A methodology to compute the statistical fault coverage of small delays due to opens

Resistive opens in vias and interconnection lines have become an issue in modern nanometer technologies. These defects may produce small delays which are difficult to detect and may pose a reliability problem. In this paper, a statistical timing analysis framework is used to analyze the detectability of small delays due to resistive opens considering process variations. A statistical methodology to estimate the fault coverage of these defects is proposed. In the statistical timing analysis framework, process variations are considered, which have become a critical issue affecting the performance and test of nanometer digital circuits. Inter-die and intra-die process variations are considered. Using the proposed methodology, the statistical fault coverage of resistive opens producing small delays is evaluated for some ISCAS benchmark circuits.