Auto-calibrating analog timer for on-chip testing

Author

Provost, B. ; Sanchez-Sinencio, Edgar

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1999

fDate

1999

Firstpage

541

Lastpage

548

Abstract

A practical approach for generating precise and slow analog ramps to be used for time-domain analog testing and for monotonicity and histogram test of ADCs is presented. The technique uses a discrete-time adaptive scheme to calibrate the ramp generator. Two implementations of the approach are proposed: one is entirely single-ended and the second uses a pseudo-differential-based offset cancellation scheme. The first implementation has been implemented in 2 mm technology and experimental results are in agreement with simulations yielding a slope error of 1.5% and distortion of 0.2%

Keywords

analogue-digital conversion; automatic test equipment; calibration; fault diagnosis; integrated circuit testing; measurement errors; ramp generators; timing circuits; ADC; analog ramps; autocalibrating analog timer; discrete-time adaptive scheme; histogram test; monotonicity; on-chip testing; pseudo-differential-based offset cancellation; ramp generator; time-domain analog testing; Analog circuits; Bandwidth; Circuit faults; Circuit testing; Delay; Filters; Frequency domain analysis; Signal generators; System testing; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805778

Filename

805778