Optimal stall insertion with timing skew adjustment for tunable LSIs

With the advance of process technologies, delay variation becomes relatively larger. As a result, it becomes difficult to improve a performance such as a clock frequency in conventional worst-case design. A post-silicon approach is one of the promising approaches to overcome this serious problem. In this paper, two techniques are introduced and combined: The first technique, named the stall insertion, is to insert pauses, and shift all the following operation schedules by one or more control steps. The second technique, named the timing skew adjustment, is a temporal difference of the arrival of clock signals at registers. This paper proposes a novel datapath which is tuned by the stall insertion with the timing skew adjustment after the fabrication. The tuned datapath in proposed design can be expected to operate correctly with minimum degradation while keeping clock period unchanged. Since the stall insertion degrades latency, the stall minimization problem is formulated incorporating with timing skew optimization. Two solution algorithms are presented: one is a mixed integer linear programming (MILP) formulation, and the other is the repetition of skew adjustability test. Experimental results show the effectiveness of our MILP.