Title :
Logic fault test simulation environment for IP core-based digital systems
Author :
Assaf, Mansour H. ; Moore, Leslie-Ann ; Das, Sunil R. ; Petriu, Emil M. ; Biswas, Satyendra N. ; Hossain, Altaf
Author_Institution :
Inf. Commun. Technol., Univ. of Trinidad & Tobago, Arima, Trinidad and Tobago
Abstract :
A logic fault test simulation environment for core-based digital systems is proposed in this paper. The simulation environment emulates a typical built-in self-test (BIST) environment with test pattern generator that sends its outputs to a circuit under test (CUT) and the output streams from the CUT are fed into a response data analyzer. The developed simulator is suitable for testing digital IP cores. The paper describes in details the test architecture and application of the logic fault simulator. Some partial simulation results on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided.
Keywords :
automatic test pattern generation; built-in self test; circuit simulation; fault diagnosis; industrial property; logic testing; system-on-chip; BIST environment; IP core-based digital system; built-in self-test; circuit under test; core-based system-on-chip; data analyzer; logic fault test simulation environment; sequential benchmark circuit; test pattern generator; Analytical models; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Digital systems; Logic testing; System testing; Test pattern generators;
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2009.5235951
