Investigation into the Complexity versus Performance of the DC Bus in a Voltage Fed Converter

Low impedance dc busses are of utmost importance in voltage fed converters and work in conjunction with the capacitor banks in order to maintain a stable supply voltage. In this paper several low inductance dc bus layouts are discussed Their performance versus their constructional complexity is investigated. Experimental measurements are used to describe the performance. It is shown that it is possible to increase performance through an increase in layout complexity although the relationship between these two is not linear.