Logic Transformations by Multiple Wire Network Addition

This paper presents an important improvement in the current capabilities of existing redundancy addition and removal (RAR) techniques for digital circuits logic optimization. In this work we present a new efficient way of finding all the possible logic addition transformations that allow the removal of a given selected wire in the circuit. All the possible points in the circuit where the addition can be performed and all the possible transformations, involving multiple wires, in each of those points are identified. We prove the necessary and sufficient conditions for the existence of such transformations. RAR algorithms use these possible sets of transformations for different optimizations, like area or timing, which have been shown to be very effective in previous works. Improving the core of these algorithms is the key to improve the RAR optimization methods themselves.