DocumentCode :
3330684
Title :
High-performance and low-bandwidth architecture of H.264 motion estimation circuit for 1080HD video
Author :
Kim, Soojin ; Chang, Hoyoung ; Lee, Seonyoung ; Cho, Kyeongsoon
Author_Institution :
Dept. of Electron. & Inf. Eng., Hankuk Univ. of Foreign Studies, Yongin, South Korea
fYear :
2009
fDate :
2-5 Aug. 2009
Firstpage :
1110
Lastpage :
1113
Abstract :
This paper presents a high-performance and low-bandwidth architecture of H.264 integer-pixel motion estimation circuit for 1080HD video. The proposed circuit supports 7 kinds of variable block sizes and generates 41 motion vectors. We propose a new motion estimation algorithm and circuit architecture to improve the processing speed and reduce the memory bandwidth. The implemented circuit based on the proposed algorithm and architecture can process 60 image frames per second for 1080HD video at the operating frequency of 45.5 MHz with smaller bandwidth requirement compared to other approaches.
Keywords :
code standards; high definition video; motion estimation; video coding; 1080HD video; H.264 motion estimation circuit; frequency 45.5 MHz; low-bandwidth architecture; Bandwidth; Circuit synthesis; Frequency synthesizers; Libraries; Motion estimation; PSNR; Region 2; SDRAM; Testing; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
ISSN :
1548-3746
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2009.5235962
Filename :
5235962
Link To Document :
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