Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool

Asynchronous digital design approach liberates VLSI systems from clock signal and offers potential for low power and high performance design methods. Due to lack of commercial CAD tools, asynchronous circuit design has not been regarded with favor. To alleviate the situation, a SystemC library is developed as an extension to the existing SystemC language to enable asynchronous circuit description at the highest level of abstraction. A tool has been developed which extracts optimized control and data flow graphs from the high level description. Also novel architectural asynchronous synthesis algorithms were proposed to generate optimized asynchronous circuit from the extracted data-flow graphs. The proposed library enables the modeling and designing of efficient asynchronous circuits at a high level without having to deal with details of asynchronous implementation. Extracted structures are produced in well-defined form that can easily be used for synthesis purposes, verification or test generation. And finally proposed synthesis tool produces asynchronous circuits with minimum required resources. Results are given by using some high-level synthesis benchmark circuits.