A novel design methodology to optimize the speed and power of the CNTFET circuits

Carbon nanotubes with their superior properties have proved to be a potential alternative device to CMOS. In this paper, circuit optimization methods for high performance and low power CNFEFT circuit are proposed. The proposed design methods for CNTFET circuit address how to decide the optimum CNTFET parameters such as pitch, diameter, number of CNTs (carbon nanotube), optimum fan-out factor and logical efforts to deliver the minimum power-delay product. The proposed method makes it possible to accomplish 56% dynamic power reduction and 22% less delay by optimizing the pitch, number of CNTs, fan-out factor, and logical efforts compared to the circuits that are not optimized and screening effects are ignored.