A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data

Author

Butler, Kenneth M.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1999

fDate

1999

Firstpage

839

Lastpage

847

Abstract

Monolithic ICs are growing so large that tester capacity is rapidly becoming a problem. There are also a number of “stored pattern” test methods which vie for limited tester resources. From a quality perspective, how do we best allocate tester memory or time? In this paper, the SEMATECH Test Methods data are used to examine this important question

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; automatic test equipment; fault diagnosis; integrated circuit testing; logic testing; ASIC; CMOS IC; SEMATECH test methods; defect detection; monolithic IC; optimised pattern; scan IDDQ testing; scan delay testing; scan stuck at testing; stored pattern; test quality; tester memory; tester scan memory; Application specific integrated circuits; Circuit simulation; Circuit testing; Delay; Instruments; Integrated circuit testing; PROM; Predictive models; Resource management; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805815

Filename

805815

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3330980