Analysis of the electrical performance of multi-coupled high-speed interconnects for SoP

In this work, we present an efficient methodology for designing and evaluating the performance of current and future multi-Gb/s chip-to-chip interconnects for Systems on Package (SoP). We analyze the coupling between neighboring stripline and microstrip lines in single ended and differential configurations. Furthermore, the method also considers conductor and dielectric losses. In order to obtain the system bandwidth and area efficiency, an exhaustive analysis of downscaled versions of current SoP interconnects was carried out. This analysis also allowed to find the optimal structure for given specifications (e.g. interconnects density, minimum bandwidth, and transmission line length). Experimentally validated 2D simulators and PDA (peak distortion analysis) tools were used in this process.