On-line fault detection in DSP circuits using extrapolated checksums with minimal test points

In this paper, we propose a novel concurrent error detection scheme for linear digital variable systems that significantly reduces the hardware overhead of the detection circuitry. A new theory of extrapolated checksums has been developed. A novel test point selection algorithm has been proposed to select the minimal set of test points without compromising fault coverage. Techniques for selecting code vectors (to compute checksums) and designing error detection circuitry have been discussed. Experimental results indicate significant hardware reduction in the error detection circuitry