DocumentCode
3331172
Title
A10-GHz 0.88-mW low-phase-noise CMOS VCO
Author
Syu, Jin-Rong ; Lin, Zhi-Ming
Author_Institution
Grad. Inst. of Integrated Circuit Design, Nat. Changhua Univ. of Educ., Changhua, Taiwan
fYear
2009
fDate
2-5 Aug. 2009
Firstpage
1063
Lastpage
1066
Abstract
In this paper, a 1.2-V 10-GHz low-power low-noise VCO is designed and fabricated in a 0.18 mum CMOS process. By using noise-reduction techniques associated with the current-reused structure, the VCO can achieve lower power consumption and phase noise. The simulated power consumption is 0.88-mW. The simulated phase noise is-114.8-dBc/Hz at 1-MHz offset frequencies. The attained FOM is-191.
Keywords
CMOS integrated circuits; low-power electronics; phase noise; voltage-controlled oscillators; FOM; VCO design; VCO fabrication; current-reused structure; frequency 1 MHz; frequency 10 GHz; low-phase-noise CMOS VCO; noise-reduction technique; power 0.88 mW; size 0.18 mum; voltage 1.2 V; CMOS process; Capacitors; Circuit noise; Energy consumption; Frequency; MOS devices; Phase noise; Tail; Tuning; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location
Cancun
ISSN
1548-3746
Print_ISBN
978-1-4244-4479-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2009.5235985
Filename
5235985
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