An on-line BISTed SRAM IP core

Author

Lobetti-Bodoni, M. ; Pricco, Alessio ; Benso, Alfredo ; Chiusano, Silvia ; Prinetto, Paolo

Author_Institution

Castelletto di Settimo Milanese, Italtel SpA, Milan, Italy

fYear

1999

fDate

1999

Firstpage

993

Lastpage

1000

Abstract

In digital systems design, strict reliability constraints usually impose very low fault latency and high degree of fault detection of permanent and transient faults. In particular, memory modules, as either devices or IP cores, appeared as one of the most critical parts. This paper presents an advanced on-line memory BIST architecture implemented as an IP core developed for telecommunication applications. A fault latency reduction architecture, a code-based fault detection scheme, and an architecture-based fault avoidance have been composed to meet the required reliability constraints

Keywords

SRAM chips; built-in self test; error correction codes; fault tolerance; integrated circuit reliability; integrated circuit testing; logic testing; architecture-based fault avoidance; code-based fault detection scheme; data fault tolerance; design constraints; fault latency reduction architecture; global architecture; logic fault tolerance; on-line BISTed SRAM IP core; on-line memory BIST architecture; reliability constraints; transient faults; Asynchronous transfer mode; Availability; Built-in self-test; Delay; Fault detection; Memory architecture; Pulp manufacturing; Random access memory; System testing; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805832

Filename

805832