A low area pipelined 2-D DCT architecture for JPEG encoder

In this paper, a novel architecture for two-dimensional discrete cosine transform (2-D DCT) is proposed. The 2-D DCT calculation exploits the separability property and allows row-column decomposition by using 2 successive one-dimensional (1-D) transforms, whose intermediate results are transposed with a parallel transposition memory. High operating frequency can be reached and pipeline technique is adopted by additional SIPO, PISO and register banks. Moreover, the 2-D DCT architecture can be used as an inverse DCT by aiding a simple control circuitry. Compared with other implementations, our proposed architecture exhibits an operation frequency of 210 MHz and costs only 30879 equivalent gates. The proposed low area pipelined 2-D DCT architecture can be modularized and suitably reused in many image and video codec systems. The final layout of an application to our JPEG encoder for grayscale images is carried out in a 0.13 mum CMOS technology.