DocumentCode
3331225
Title
A machine learning-based approach for thread mapping on transactional memory applications
Author
Castro, Márcio ; Góes, Luís Fabrício Wanderley ; Ribeiro, Christiane Pousa ; Cole, Murray ; Cintra, Marcelo ; Méhaut, Jean-François
Author_Institution
INRIA - LIG Lab., Grenoble Univ., Grenoble, France
fYear
2011
fDate
18-21 Dec. 2011
Firstpage
1
Lastpage
10
Abstract
Thread mapping has been extensively used as a technique to efficiently exploit memory hierarchy on modern chip-multiprocessors. It places threads on cores in order to amortize memory latency and/or to reduce memory contention. However, efficient thread mapping relies upon matching application behavior with system characteristics. Particularly, Software Transactional Memory (STM) applications introduce another dimension due to its runtime system support. Existing STM systems implement several conflict detection and resolution mechanisms, which leads STM applications to behave differently for each combination of these mechanisms. In this paper we propose a machine learning-based approach to automatically infer a suitable thread mapping strategy for transactional memory applications. First, we profile several STM applications from the STAMP benchmark suite considering application, STM system and platform features to build a set of input instances. Then, such data feeds a machine learning algorithm, which produces a decision tree able to predict the most suitable thread mapping strategy for new unobserved instances. Results show that our approach improves performance up to 18.46% compared to the worst case and up to 6.37% over the Linux default thread mapping strategy.
Keywords
Linux; concurrency control; decision trees; learning (artificial intelligence); microprocessor chips; multiprocessing systems; Linux; STAMP benchmark suite; decision tree; machine learning based approach; memory contention; memory hierarchy; memory latency; modern chip multiprocessors; software transactional memory applications; thread mapping; Decision trees; Instruction sets; Linux; Machine learning; Multicore processing; Prediction algorithms; Runtime; machine learning; software transactional memory; thread mapping;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing (HiPC), 2011 18th International Conference on
Conference_Location
Bangalore
Print_ISBN
978-1-4577-1951-6
Electronic_ISBN
978-1-4577-1949-3
Type
conf
DOI
10.1109/HiPC.2011.6152736
Filename
6152736
Link To Document