Title :
Using Verilog simulation libraries for ATPG
Author :
Wohl, Peter ; Waicukauski, John
Author_Institution :
Synopsys Inc., Williston, VT, USA
Abstract :
Significant engineering effort is invested into coding libraries for automatic test pattern generation (ATPG) and verifying their equivalence with corresponding “golden” simulation libraries. These tasks are greatly simplified by using the methodology and the ATPG described in this paper. Simulation libraries are read-in with little or no recoding. Various structural and some behavioral Verilog constructs are automatically converted into efficient gate-level models for ATPG
Keywords :
automatic test pattern generation; automatic test software; fault simulation; hardware description languages; ATPG; IC design flow; Verilog simulation libraries; behavioral Verilog constructs; coding libraries; efficient gate-level models; netlist reader; structural Verilog constructs; test debug; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit simulation; Debugging; Emulation; Hardware design languages; Libraries; Microcontrollers; Timing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805834
