DocumentCode
3331417
Title
Addressable test ports an approach to testing embedded cores
Author
Whetsel, Lee
Author_Institution
Texas Instrum. Inc., TX, USA
fYear
1999
fDate
1999
Firstpage
1055
Lastpage
1064
Abstract
Intellectual property (IP) core reuse is an emerging design style that will significantly accelerate the complexity of ICs. IP cores are predesigned circuit functions that can be selected from a library and integrated into system ICs to quickly provide highly complex silicon solutions. Low cost, efficient testing of system ICs designed with IP cores will be challenging
Keywords
analogue integrated circuits; automatic test equipment; automatic testing; digital integrated circuits; embedded systems; industrial property; integrated circuit testing; mixed analogue-digital integrated circuits; parallel architectures; peripheral interfaces; RAM; addressable test ports; analogue circuit; core sharing; digital ic; embedded cores; mixed signal circuit; parallel scan; parallel testing; system IC; test pattern architecture; testing; Circuit testing; Communication system control; Fabrics; Instruments; Integrated circuit interconnections; Integrated circuit testing; Intellectual property; Libraries; Life estimation; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1999. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-5753-1
Type
conf
DOI
10.1109/TEST.1999.805839
Filename
805839
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