Is DFT right for you?

Author

Johnson, Jim

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1999

fDate

1999

Firstpage

1090

Lastpage

1097

Abstract

In the past 10 years or more several papers have been published to evaluate what economical cost is associated with adding “Design For Test” techniques to a design. Is Cost the only factor that needs to be examined to make a decision on adding or not adding DFT to your chip? The objective of this paper is to describe the main criteria and trade-offs of adding DFT to a design and models to help justify the overall cost impact from design to volume production. This paper will give a description of the models used and the results obtained. The objective to developing the Motorola DFT analysis model is to take all major criteria into consideration in addition to cost to decide if DFT should be implemented. The model will use both scan based testing for logic and (Built In Self Test) BIST for memories as its main DFT techniques

Keywords

built-in self test; design for testability; integrated circuit economics; integrated circuit testing; integrated memory circuits; production testing; BIST; Built In Self Test; DFT; Design For Test; Motorola DFT analysis model; economical cost; memories; trade-offs; Automatic testing; Built-in self-test; Chip scale packaging; Costs; Debugging; Design for testability; Failure analysis; Paper technology; Production; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805843

Filename

805843