A low-power multiplication algorithm for signal processing in wireless sensor networks

Multiplication is at the core of many data processing tasks and saving power at the multiplication level can significantly impact the lifetime of a wireless sensor network. This paper introduces a novel light-weight low-power multiplication algorithm which is tailored for sensor nodes featuring low-end microcontrollers. These microcontrollers might have no hardware multiplier, or feature a fixed-point hardware multiplier which incurs significant energy overhead when enabled. The proposed algorithm aims to reduce the number of add operations during multiplication by rounding any sequence of 1´s in the fractional part. The applied rounding decreases the number of instruction cycles, and reduces the memory storage without increasing the code complexity or sacrificing accuracy. Simulation results show that the proposed algorithm achieves up to 17% power saving and 16% increase in speed, with only 1% accuracy loss compared to Horner´s algorithm. The effectiveness of the algorithm was demonstrated by implementing a finite impulse response (FIR) using the proposed method. The new multiplication method has been validated experimentally using the eZ430-RF2500 wireless sensor board.