Hardware implementation of matrix inversion for Raptor decoder on embedded system

Raptor codes have been proven very suitable for mobile multimedia content delivery, and yet they have not been investigated in the context of embedded systems where the energy dissipation is as important as the timing performance. At the heart of Raptor codes is the matrix inversion operation. This paper proposes a dedicated hardware block, for two matrix inversion algorithms, as a part of Raptor decoder implemented on a system on a chip (SoC) platform with a soft-core embedded processor. The performance, energy profile and resource implication are analyzed and compared with a pure software implementation.