DocumentCode :
3331550
Title :
High Time For High Level ATPG
Author :
Iyer, Mahesh A.
Author_Institution :
Synopsys, Inc.
fYear :
1999
fDate :
1999
Firstpage :
1112
Lastpage :
1112
Keywords :
Automatic test pattern generation; Automatic testing; Circuit synthesis; Computer aided manufacturing; Crosstalk; Design automation; Hardware design languages; National electric code; Sun; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1999. Proceedings. International
ISSN :
1089-3539
Print_ISBN :
0-7803-5753-1
Type :
conf
DOI :
10.1109/TEST.1999.805847
Filename :
805847
Link To Document :
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