A novel design technique for soft error hardening of Nanoscale CMOS memory

Tolerance to soft errors has become a strict requirement in today´s nanoscale CMOS designs. This paper proposes a new hardening design technique for CMOS memory cell at 32nm feature size. The proposed hardened memory cell overcomes the problems associated with the previous designs by utilizing novel access and refreshing mechanisms. Simulation shows that the data stored in the proposed hardened memory cell does not change even for a transient pulse with more than two times higher charge than the conventional memory cell and achieves a 55% reduction in power delay product compared to the DICE cell, thus achieving a significant improvement in soft error tolerance. The extensive HSPICE simulations show that the proposed memory cell is preferable over existing configurations when designing hardened memories for both high performance and soft error tolerance.