Clock cycle estimations for future microprocessor generations

Author

Fischer, P.D.

Author_Institution

SEMATECH, Austin, TX

fYear

1997

fDate

8-10 Oct 1997

Firstpage

61

Lastpage

71

Abstract

In the past 50 years, the semiconductor industry has experienced unprecedented growth. Identifying pivotal factors and technology trends in future generations will be key to understanding how we can maintain the historical growth and improve customer value. Processor performance will be one of the essential factors in this quest. This paper presents a high-level model of microprocessor clock-cycle performance. The model considers the impact of interconnect technology, device and circuit technology, along with architectural and physical design factors, to estimate clock speeds of future microprocessors

Keywords

clocks; integrated circuit design; integrated circuit modelling; integrated circuit technology; microprocessor chips; technological forecasting; architectural design factors; circuit technology; clock cycle estimations; customer value; future microprocessor generations; high-level model; interconnect technology; physical design factors; semiconductor industry; technology trends; Clocks; Computer aided instruction; Computer architecture; Delay; Electronic mail; Electronics industry; Frequency estimation; Integrated circuit interconnections; Microprocessors; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1094-7116

Print_ISBN

0-7803-4276-3

Type

conf

DOI

10.1109/ICISS.1997.630247

Filename

630247