Design techniques of P-Type CMOS circuits for gate-leakage reduction in deep sub-micron ICs

With rapid technology scaling, the proportion of the static power catches up with dynamic power gradually. To decrease leakage power is becoming more and more important in low-power design. Base on the pact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, p-type complementary pass-transistor logic (P-CPL) and p-type differential cascade voltage switch logic (P-DCVSL) are proposed to reduce the static power in this paper. For an example, two full adders based on P-CPL and P-DCVSL circuits are verified. All circuits are simulated using 130 nm, 65 nm and 32 nm CMOS processes. Their delay, power, and PDP are compared. Simulation results show that the P-CPL full adder consumes about 60%-80% of the dissipated energy of the static CMOS and CPL ones at 200 MHz. The P-DCVSL full adder consumes 80%-90% of the dissipated energy of the DCVSL one at 200 MHz.