DocumentCode :
3332280
Title :
Performance of CNFET SRAM cells under diameter variation corners
Author :
Zhang, Zhe ; Liu, Yanmin ; Nyathi, Jabulani ; Delgado-Frias, José G.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fYear :
2009
fDate :
2-5 Aug. 2009
Firstpage :
547
Lastpage :
550
Abstract :
In this paper three carbon nanotube FET based static memory cells are compared on read and write delays, energy consumption, and performance under diameter variation corners. The carbon nanotube FET is currently considered to be the possible ldquobeyond CMOSrdquo device due to its1-D transport properties that include low carrier scattering and ballistic transport. The memory cells are classified by their transistor count (6-, 7- and 8-transistor cell.) Under a nominal diameter of 1.51 nm, the 8-T cell has the lowest delay and energy consumption of 3.7 ps and 0.348 fJ, respectively. Simulations with transistor diameter variations show that small n-type device diameters result in significantly slow read and write delays. The 8-transistor cell dissipates the least energy when the transistor diameters range from 1.369 nm to 1.659 nm.
Keywords :
SRAM chips; ballistic transport; carbon nanotubes; field effect integrated circuits; nanotube devices; 1D transport properties; CNFET SRAM cells; ballistic transport; carbon nanotube FET; carrier scattering; size 1.51 nm; static memory cells; CMOS technology; CNTFETs; Carbon nanotubes; Delay; FinFETs; MOSFETs; Power dissipation; Random access memory; Read-write memory; Semiconductivity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
ISSN :
1548-3746
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2009.5236035
Filename :
5236035
Link To Document :
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