A transmission gate flip-flop based on dual-threshold CMOS techniques

In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce the leakage power is dual-threshold techniques. Low-threshold transistors are assigned to critical paths of the circuits to enhance the performance, while high-threshold transistors are assigned to non-critical paths to reduce the leakage current. This paper proposes a new transmission gate flip-flop based on dual-threshold CMOS technique to reduce its leakage power. Simulation results show that the proposed transmission gate dual-threshold flip-flop saves 20-30% power and 40-50% leakage power compared with the single-threshold transmission gate one and gate-length biasing one, respectively. The proposed flip-flop is an excellent candidate for low-power VLSI designs in deep sub-micro ICs.