Floating-Gate energy recovery logic

In this paper, a new energy recovery logic based on floating gate transistors is presented. Floating-gate energy recovery logic (FGERL) achieves small transistor count and low voltage operation. High voltage constraint and big transistor count are major issues in adiabatic logics. Most adiabatic approaches use complex circuitry to achieve an efficient charge recovery, requiring high voltage from the power clocking circuits. Reducing transistor count reduces voltage requirement and static dissipation; less dissipating components, less power dissipated. In addition, this proposal is easy to design and implement due to its simplified architecture and single power clock scheme.