• DocumentCode
    3332487
  • Title

    Circuit Simulation and Timing Verification based on MOS/LSI Mask Information

  • Author

    Akino, Toshiro ; Shimode, Masfumi ; Kurashige, Yukinaga ; Negishi, Toshio

  • Author_Institution
    Matsushita Electronics Corporation, Kyoto, Japan
  • fYear
    1979
  • fDate
    25-27 June 1979
  • Firstpage
    88
  • Lastpage
    94
  • Abstract
    A mask analysis program for MOS/LSI mask layout data has been developed. This program converts all the mask layout data in one chip LSI into the corresponding circuit schema. A partitioning method for the large random logic circuit divides it into small subcircuits. It is shown that this method takes full advantage of the savings both in computer time and computer storage for the circuit simulation and timing verification of the random logic circuit having more than 500 active devices.
  • Keywords
    Circuit analysis computing; Circuit optimization; Circuit simulation; Computational modeling; Information analysis; Large scale integration; Logic circuits; Logic design; Logic devices; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1979. 16th Conference on
  • Type

    conf

  • DOI
    10.1109/DAC.1979.1600093
  • Filename
    1600093
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3332487