DocumentCode
3332492
Title
Speedup of a large word-width high-speed asynchronous Multiply and Accumulate unit
Author
Zhou, Liang ; Smith, Scott C.
Author_Institution
Dept. of Electr. Eng., Univ. of Arkansas, Fayetteville, AR, USA
fYear
2009
fDate
2-5 Aug. 2009
Firstpage
499
Lastpage
502
Abstract
This paper develops a new high-speed architecture for asynchronous multiply and accumulate (MAC) feedback circuitry, resulting in a speedup of 1.72 over the previous fastest 72+32times32 asynchronous MAC in the literature.
Keywords
asynchronous circuits; circuit feedback; multiplying circuits; pipeline arithmetic; NULL convention logic; asynchronous MAC; gate-level piplining; multiply and accumulate feedback circuitry; speedup; Adders; Delay; Feedback circuits; Feedback loop; Feedforward systems; Logic gates; Pipeline processing; Signal generators; Throughput; USA Councils; Gate-Level Piplining (GLP); NULL Convention Logic (NCL); NULL Cycle Reduction (NCR); computer arithmetic;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location
Cancun
ISSN
1548-3746
Print_ISBN
978-1-4244-4479-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2009.5236047
Filename
5236047
Link To Document