DocumentCode
3332505
Title
LSI Layout Checking Using Bipolar Device Recognition Technique
Author
Chang, C.S.
Author_Institution
IBM Data Systems Division, East Fishkill Hopewell Junction, NY
fYear
1979
fDate
25-27 June 1979
Firstpage
95
Lastpage
101
Abstract
Layout errors often result in nonfunctioning devices that still adhere to all layout tolerance rules. Reported here is a method for locating such errors in addition to the tolerance rule checking.
Keywords
Bipolar integrated circuits; Data systems; Integrated circuit layout; Ion implantation; Large scale integration; Resistors; Schottky barriers; Schottky diodes; Shape; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1979. 16th Conference on
Type
conf
DOI
10.1109/DAC.1979.1600094
Filename
1600094
Link To Document