Design of low power precharge-evaluation based one bit adder cell

Rapid changes in SoC power issues has mandated the reconsideration of design methodologies throughout the flow to account for power related effects. This led to the evolution of various design methods to meet power budgets while designing various modern age information systems and computers. In this work, we present a precharge/evaluation based carry generation logic circuit for adders which shows a good improvement in power consumption, exploiting different power saving techniques for the implementation, particularly reducing switching activity and operand pre-computation. Additionally sum logic exploits ldquodata sensingrdquo technique resulting in faster speed and lower transistor count. Design has been implemented in 90 nm process, showing 30% improvement in performance and 35% reduction in total dynamic power compared to conventional one.