A circuit design and fabrication approach to address global process variation

This paper proposes a new approach for reducing the consequences of global process variation and improving integrated circuit yield. In the proposed technique, a design of a given circuit block is optimized for multiple process corners, giving rise to multiple sub-designs. The sub-designs are constructed such that all can be implemented using the same front-end-of-the-line mask steps, and having back-end-of-the-line processing differing by as few as one mask step (e.g., the Via1 layer). During fabrication, in-line measurements made after the first level of metal deposition determine which sub-design is fabricated through the appropriate selection of the mask step variant. The technique allows for per-wafer or per-reticle circuit customization based on the wafer´s or reticle´s process parameters. A tapered buffer chain is investigated as an example of the technique. Simulation results show yield improvements of up to 20% and reductions in power dissipation up to 18%.