Testing of MOS Combinational Networks - A Procedure for Efficient Fault Simulation and Test Generation

The increasing use of large and very large scale integration (LSI and VLSI) have introduced many difficulties in testing large logic networks. This generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks, with and without fan-in, fan-out constraints, were described in previous papers. Procedures for efficient fault simulation and test generation will be presented here. First, a basic cell model will be introduced. Next, procedures for generating a complete fault detection set for the complex cell will be given. Both minimal and near-minimal solutions will be presented for both fan-out free and arbitrary cells respectively. The efficiency of this technique will be compared with conventional testing techniques (e.g. N-dimensional path sensitization automatic test generator with a parallel fault simulator) and the results will be reported. Finally, some future work problems will be introduced and the application of this technique for improving LSI and VLSI testability will be discussed.