A ΔΣ CMOS ADC with 80-dB dynamic range and 31-MHz signal bandwidth

A new SigmaDelta modulator architecture is proposed that shapes DAC mismatches in a manner similar to quantization noise shaping, allowing operation with low oversampling ratios and compact logic. The concept is demonstrated in a fourth-order cascaded system running at a clock frequency of 500 MHz and digitizing input frequencies as high as 31 MHz with 80-dB dynamic range. Fabricated in 90-nm CMOS technology, the prototype provides a peak signal-to-(noise+distortion) ratio of 70 dB at 31 MHz while consuming 140 mW from a 1.2-V supply.