A pipelined ADC architecture for low-voltage CMOS applications

A pipelined analog to digital converter (ADC) architecture is introduced for VT +2V_dsat supply voltage operation. The pipeline stage amplifier uses an active bootstrapped gain enhancement technique to produce greater than 70dB of gain in a single stage amplifier without a full cascode to maximize output swing. Low-voltage sampling is achieved with reset-amplifier based switching. The pipeline architecture is used to design and implement a 10-bit fully differential ADC in an 0.35 mum CMOS process. The fabricated ADC achieves greater than 9 effective number of bits (ENOB) at supply voltages as low as 0.64 V with a process VT + 2V_dsat of 0.85 V by using a bulk-source driven threshold lowering technique. The converter achieves 8.84 ENOB at sampling rates as high as 1MSPS with a 0.875 V supply voltage.