Title :
Optimal Layout of CMOS Functional Arrays
Author :
Uehara, Takao ; Vancleemput, William M.
Author_Institution :
FUJITSU Laboratories Ltd
Abstract :
This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented.
Keywords :
CMOS technology; Computer science; Integrated circuit synthesis; Laboratories; Large scale integration; Libraries; Logic arrays; Logic functions; Network synthesis; Semiconductor device modeling;
Conference_Titel :
Design Automation, 1979. 16th Conference on
DOI :
10.1109/DAC.1979.1600120
