An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC

Author

Balagopal, Sakkarapani ; Ay, Suat U.

Author_Institution

Electr. & Comput. Eng., Univ. of Idaho, Moscow, ID, USA

fYear

2009

fDate

2-5 Aug. 2009

Firstpage

373

Lastpage

376

Abstract

An on-chip ramp generator was developed for single-slope look-ahead ramp (SSLAR) analog-to-digital converter (ADC) integrated in a column-parallel CMOS image sensor. Ramp generator is the central part of a new ADC algorithm which uses modified single-slope ramp (SSR) ADC timing. Ramp block designed such a way that it allows wide output voltage ranges as well as code hopping, code fall back and look-ahead operations in column-parallel ramp ADC. Ramp generator was fabricated using 0.5 mum, 2P3M CMOS technology. Ramp generator composes of 10-bit synchronous counter, switched-capacitor based voltage steering circuits, output buffer and logic circuits. Effective layout area of ramp generator is 0.3 mm².

Keywords

CMOS image sensors; analogue-digital conversion; logic circuits; ramp generators; 2P3M CMOS technology; ADC algortihm; SSLAR analog-to-digital converter; code hopping; column-parallel CMOS image sensor; logic circuits; look-ahead operations; modified single-slope ramp ADC timing; on-chip ramp generator; output buffer; single-slope look ahead ramp ADC; size 0.5 mum; switched-capacitor based voltage steering circuits; synchronous counter; Algorithm design and analysis; Analog-digital conversion; CMOS image sensors; CMOS technology; Clocks; Counting circuits; Latches; Silicon; Topology; Voltage; CMOS APS; CMOS image sensors; column parallel ADC; ramp generator; single-slope look-ahead ramp ADC; single-slope ramp ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Conference_Location

Cancun

ISSN

1548-3746

Print_ISBN

978-1-4244-4479-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2009.5236076

Filename

5236076